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PRELIMINARY
FEMTOCLOCKSTM CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
ICS844256
GENERAL DESCRIPTION
The ICS844256 is a Cr ystal-to-LVDS Clock Synthesizer/Fanout Buffer designed for SONET HiPerClockSTM and Gigabit Ether net applications and is a member of the HiperClockSTM family of High Perfor mance Clock Solutions from IDT. The output frequency can be set using the frequency select pins and a 25MHz crystal for Ethernet frequencies, or a 19.44MHz crystal for SONET. The low phase noise characteristics of the ICS844256 make it an ideal clock for these demanding applications.
FEATURES
* Six LVDS outputs * Crystal oscillator interface * Output frequency range: 62.5MHz to 622.08MHz * Crystal input frequency range: 15.625MHz to 25.5MHz * RMS phase jitter at 125MHz, using a 25MHz crystal (1.875MHz to 20MHz): 0.48ps (typical) * Full 3.3V or 3.3V core, 2.5V output supply mode * 0C to 70C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
Function
IC S
SELECT FUNCTION TABLE
Inputs FB_SEL 0 0 0 0 1 1 1 1 N_SEL1 0 0 1 1 0 0 1 1 N_SEL0 0 1 0 1 0 1 0 1 M Divide 25 25 25 25 32 32 32 32 N Divide 1 2 4 5 1 2 4 8 M/N 25 12.5 6.25 5 32 16 8 4
BLOCK DIAGRAM
Q0 nQ0 PLL_BYPASS
Pullup
PIN ASSIGNMENT
VDDO VDDO nQ2 Q2 nQ1 Q1 nQ0 Q0 PLL_BYPASS VDDA VDD FB_SEL 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Q3 nQ3 Q4 nQ4 Q5 nQ5 N_SEL1 GND GND N_SEL0 XTAL_OUT XTAL_IN
Q1
1
XTAL_IN
nQ1
OSC
XTAL_OUT
PLL
0
Output Divider
Q2 nQ2 Q3
Feedback Divider
FB_SEL N_SEL1 N_SEL0
Pulldown Pullup Pullup
ICS844256
24-Lead TSSOP, E-Pad 4.40mm x 7.8mm x 0.90mm body package G Package Top View
nQ3 Q4 nQ4 Q5 nQ5
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
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PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5, 6 7, 8 9 10 11 12 13, 14 15, 18 16, 17 19, 20 21, 22 23, 24 Name VDDO nQ2, Q2 nQ1, Q1 nQ0, Q0 PLL_BYPASS VDDA VDD FB_SEL XTAL_IN, XTAL_OUT N_SEL0 N_SEL1 GND nQ5, Q5 nQ4, Q4 nQ3, Q3 Power Output Output Output Input Power Power Input Input Input Pullup Type Description Output supply pins. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Selects between the PLL and crystal inputs as the input to the dividers. When LOW, selects PLL. When HIGH, selects XTAL_IN, XTAL_OUT. LVCMOS / LVTTL interface levels. Analog supply pin. Core supply pin. Pulldown Feedback frequency select pin. LVCMOS/LVTTL interface levels. Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Pullup Output frequency select pin. LVCMOS/LVTTL interface levels. Power supply ground. Output Output Output Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
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PRELIMINARY
CRYSTAL FUNCTION TABLE
Inputs XTAL (MHz) 20 20 20 20 21.25 24 24 24 24 25 25 25 25 25.5 15.625 18.5625 18.75 18.75 18.75 18.75 19.44 19.44 19.44 19.44 19.53125 19.53125 19.53125 19.53125 20 FB_SEL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 N_SEL1 0 0 1 1 1 0 0 1 1 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 N_SEL0 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1 M 25 25 25 25 25 25 25 25 25 25 25 25 25 25 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 500 500 500 500 531.25 600 600 60 0 60 0 625 625 625 625 637.5 500 594 600 600 600 600 622.08 622.08 622.08 622.08 625 625 625 62 5 640 Function VCO (MHz) N 1 2 4 5 5 1 2 4 5 1 2 4 5 4 8 8 1 2 4 8 1 2 4 8 1 2 4 8 8 Output (MHz) 500 250 125 100 106.25 600 300 150 12 0 625 312.5 156.25 12 5 159.375 62.5 74.25 600 300 150 75 622.08 311.04 155.52 77.76 625 312.5 156.25 78.125 80
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PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current 4.6V -0.5V to VDD + 0.5V 10mA 15mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, JA 24 Lead TSSOP, EPad 32.1C/W (0 mps) Storage Temperature, TSTG -65C to 150C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 VDD - 0.08 3.135 Typical 3.3 3.3 3.3 132 8 120 Maximum 3.465 VDD 3.465 Units V V V mA mA mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 VDD - 0.07 2.375 Typical 3.3 3.3 2.5 125 7 115 Maximum 3.465 VDD 2.625 Units V V V mA mA mA
TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 3.3V5%
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage Input High Current FB_SEL PLL_BYPASS, N_SEL0, N_SEL1 FB_SEL PLL_BYPASS, N_SEL0, N_SEL1 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V Test Conditions
OR
2.5V5%, TA = 0C
TO
70C
Minimum 2 -0.3
Typical
Maximum VDD + 0.3 0.8 150 5
Units V V A A A A
-5 -150
IIL
Input Low Current
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TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDO = 3.3V5% TA = 0C TO 70C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change Test Conditions Minimum Typical 350 40 1.25 50 Maximum Units mV mV V mV
NOTE: Please refer to Parameter Measurement Information for output information.
TABLE 4E. LVDS DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VOD V OD VOS V OS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change Test Conditions Minimum Typical 350 40 1.25 50 Maximum Units mV mV V mV
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant cr ystal. 15.625 Test Conditions Minimum Typical Maximum 25.5 50 7 1 Units MHz pF mW Fundamental
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TABLE 6A. AC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter FOUT t jit(O) t sk(o) tR / tF odc Output Frequency RMS Phase Jitter (Random) Output Skew; NOTE 1, 2 Output Rise/Fall Time Output Duty Cycle 20% to 80% 125MHz, Integration Range: 1.875MHz - 20MHz Test Conditions Minimum 53.125 0.48 TBD 37 5 50 1 Typical Maximum 333.33 Units MHz ps ps ps % ms
PLL Lock Time tLOCK See Parameter Measurement Information section. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6B. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol Parameter FOUT tjit(O) t sk(o) tR / tF odc Output Frequency RMS Phase Jitter (Random) Output Skew; NOTE 1, 2 Output Rise/Fall Time Output Duty Cycle 20% to 80% 125MHz, Integration Range: 1.875MHz - 20MHz Test Conditions Minimum 53.125 0.44 TBD 400 50 1 Typical Maximum 333.33 Units MHz ps ps ps % ms
PLL Lock Time tLOCK See Parameter Measurement Information section. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
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TYPICAL PHASE NOISE AT 125MHZ @ 3.3V
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 -200 10 100 1k 10k
Gb Ethernet Filter 125MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.48ps (typical)
NOISE POWER dBc Hz
Raw Phase Noise Data
Phase Noise Result by adding Gb Ethernet Filter to raw data
100k 1M 10M 100M
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 -200 10
TYPICAL PHASE NOISE AT 125MHZ @ 3.3V/2.5V
Gb Ethernet Filter 125MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.44ps (typical)
OFFSET FREQUENCY (HZ)
NOISE POWER dBc Hz
Raw Phase Noise Data
Phase Noise Result by adding Gb Ethernet Filter to raw data
100 1k 10k 100k 1M 10M 100M
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OFFSET FREQUENCY (HZ)
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PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
VDD
SCOPE
3.3V5% POWER SUPPLY + Float GND -
VDDA VDDO
Qx
SCOPE
++ -
VDD, VDDO V DDA
Qx
LVDS
LVDS
nQx
nQx
POWER SUPPLY Float GND
3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT
nQx Qx
nQ0:nQ5 Q0:Q5
t PW
nQy Qy
t
PERIOD
tsk(o)
odc =
t PW t PERIOD
x 100%
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VDD out
80% Clock Outputs
80% VSW I N G
DC Input
LVDS
out
20% tR tF
20%
VOS/ VOS
OUTPUT RISE/FALL TIME
OFFSET VOLTAGE SETUP
VDD out
DC Input
LVDS
100
VOD/ VOD out
DIFFERENTIAL OUTPUT VOLTAGE SETUP
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ICS844256 FEMTOCLOCKSTM CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS844256 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and 0.01F bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VDDA requires that an additional10 resistor along with a 10F bypass capacitor be connected to the VDDA pin.
3.3V VDD .01F VDDA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS:
LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
OUTPUTS:
LVDS Outputs All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, we recommend that there is no trace attached.
CRYSTAL INPUT INTERFACE
The ICS844256 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using an 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_IN C1 18p X1 18pF Parallel Crystal XTAL_OUT C2 22p
FIGURE 2. CRYSTAL INPUt INTERFACE
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LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC couple capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series
VDD VCC
resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50.
VDD VCC
R1 Ro Rs Zo = 50 .1uf XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
3.3V, 2.5V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input.
2.5V or 3.3V VDD LVDS_Driv er + R1 100
-
100 Ohm Differential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
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ICS844256 FEMTOCLOCKSTM CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
PRELIMINARY
EPAD THERMAL RELEASE PATH
In order to maximize both the removal of heat from the package and the electrical perfor mance, a land patter n must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 5. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as "heat pipes". The number of vias (i.e. "heat pipes") are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor's Thermally/ Electrically Enhance Leadfame Base Package, Amkor Technology.
SOLDER PIN EXPOSED HEAT SLUG
SOLDER
PIN
SOLDER
PIN PAD
GROUND PLANE THERMAL VIA
LAND PATTERN (GROUND PAD)
PIN PAD
FIGURE 5. ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH -SIDE VIEW (DRAWING NOT TO SCALE)
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PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS844256. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS844256 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
* *
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (132mA + 8mA) = 485.1mW Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 120mA = 415.8mW
Total Power_MAX = 485.1mW + 415.8mW = 900.9mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 32.1C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.901W * 32.1C/W = 98.9C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE JA
FOR
24-LEAD TSSOP, E-PAD, FORCED CONVECTION
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 32.1C/W
1
25.5C/W
2.5
24.0C/W
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PRELIMINARY
RELIABILITY INFORMATION
TABLE 8. JAVS. AIR FLOW TABLE
FOR
24 LEAD TSSOP, E-PAD
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 32.1C/W
1
25.5C/W
2.5
24.0C/W
TRANSISTOR COUNT
The transistor count for ICS844256 is: 3887
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PACKAGE OUTLINE - G SUFFIX
FOR
24 LEAD TSSOP, E-PAD
TABLE 9. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b b1 c c1 D E E1 e L P P1 aaa bbb 0 0.076 0.10 0.50 4.30 -0.05 0.85 0.19 0.19 0.09 0.09 7. 7 0 0.127 7.80 6.40 BASIC 4.40 0.65 BASIC 0.60 0.70 5.0 3.2 8 4.50 0.22 0.90 Millimeters Minimum Nominal 24 1.10 0.15 0.95 0.30 0.25 0.20 0.16 7.90 Maximum
Reference Document: JEDEC Publication 95, MO-153
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PRELIMINARY
TABLE 10. ORDERING INFORMATION
Part/Order Number ICS844256BG ICS844256BGT ICS844256BGLF ICS844256BGLFT Marking ICS844256BG ICS844256BG ICS844256BGLF ICS844256BGLF Package 24 Lead TSSOP, E-Pad 24 Lead TSSOP, E-Pad 24 Lead "Lead-Free" TSSOP, E-Pad 24 Lead "Lead-Free" TSSOP, E-Pad Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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(c) 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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